Annotated adder_demo

Fanout is how many input pins a single output drives. An output feeding 3 gates has a fanout of 3.

Why it matters: every input pin is a tiny capacitor. Driving one is easy; driving fifty means charging fifty capacitors through one small transistor, which is slow — like one person pushing fifty shopping trolleys. So high-fanout signals get buffers inserted: a tree of amplifier cells that splits the load. The 3 × clkbuf_16 in the histogram are exactly that (_16 = very high drive strength).

A clock net is the wire carrying clk. It is special because it must reach every single flip-flop — all 16 here — and, critically, arrive at all of them at nearly the same instant. If one flop sees the edge noticeably later than its neighbour, it may capture the new value instead of the old one, and a shift register quietly corrupts itself. That spread is called clock skew, and a whole place-and-route stage ("clock tree synthesis") exists purely to minimise it. That is where clknet_1_1__leaf_clk in the netlist came from: the tool replaced your raw clk with the output of a balanced buffer tree.

Fat routing means physically wider metal wires. Wider metal has lower resistance, so less delay and less skew. Since the clock is the most timing-critical net on the chip, it is usually drawn wider than ordinary signal wires and often on a dedicated upper metal layer.

Verilog has two ways to describe hardware, and the wire/reg choice simply records which one you used.

Continuous assignment — for combinational logic:

An assign is not "compute a+b once". It means there is permanently a physical adder here whose output is welded to sum. If a changes at 3pm, sum changes at 3pm plus a few hundred picoseconds. Forever. Targets of assign must be declared wire.

Procedural block — an always block is a chunk of behaviour that re-evaluates whenever something in its trigger list changes. Inside it you may use if/else/case, which reads like software — but the synthesizer's job is to work out what circuit would produce that behaviour. Anything assigned inside an always block must be declared reg.

So on L6, parallel_out is reg purely because L10 and L12 assign it inside an always. It does also become real registers — but because of L8, not because of the word reg. On L19, sum is a wire because it is driven by assign.

The sensitivity list is the @(...) part of an always block: the list of events that wake the block up. Here it reads "re-evaluate this block when clk rises or when rst_n falls."

This exact shape is a template. The synthesizer does not reason about your code in general — it pattern-matches known idioms and swaps in the matching cell:

Async vs sync reset. Mentioning rst_n in the sensitivity list means reset acts immediately, without waiting for a clock edge — the reset wire goes physically into the flip-flop's own RESET_B pin. Had you instead written @(posedge clk) and tested rst_n inside, reset would only take effect at the next clock edge (synchronous) and would be built from a gate on the D input. Different silicon, from a one-word difference.

As for the cell name and the "16": the name decodes to d-flipflop, reset, true output, positive edge — the breakdown table is in Foundations §4. The "16" was a sanity check: your source declares 8 bits of state and instantiates the module twice, so the design must contain 8 × 2 = 16 one-bit memory cells. The netlist contains exactly 16 dfrtp_2. The ✔ meant source and silicon agree — which is the fundamental move of this whole puzzle, just run in the forward direction.

Literal syntax

The form is <width>'<base><value>.

The width is mandatory in good style because in hardware every signal has a fixed physical bit-width — there is no such thing as an unsized integer when it is made of wires. Writing 8'b0 rather than 0 says plainly: eight wires, all held at ground.

Blocking = vs non-blocking <=

This is the classic beginner cliff, so here is the concrete version. Take two flops currently holding a=1, b=0, and a clock edge arrives.

Non-blocking (<=) means: read all right-hand sides first using the OLD values, then update everything at once. So a gets old b (0) and b gets old a (1) — they swap. This is exactly what real flip-flops do: they all sample simultaneously on the edge, before any of them have updated.

Blocking (=) executes top-to-bottom like software: a becomes 0, then b reads the already-updated a and also becomes 0. No swap. Not what the hardware does.

DFF and histogram are covered in Foundations §3 and §5. Here is L11 properly, because it is genuinely the subtlest thing in the file.

Enumerate the three cases at a clock edge:

• rst_n == 0 → load zero
• rst_n == 1, en == 1 → load the shifted value
• rst_n == 1, en == 0 → the code says nothing

Notice there is no else clause at all — the if chain just ends at L13.

In software, "says nothing" means do nothing. In hardware, "the value must not change" means you have to physically build something that remembers — which is the definition of state. Verilog's rule is: if a reg is not assigned on some path through the block, it must hold its previous value.

But look at the DFF again. It has D, CLK, Q. There is no "freeze" pin. The clock is still ticking — you must never casually gate a clock, that is how you get skew and glitch bugs — so the flop will capture whatever sits on D at the next edge, unavoidably.

The only way to make Q come out unchanged is to feed Q back into D. If D already equals Q, the capture is a no-op. So the synthesizer inserts a multiplexer — a two-way switch, X = S ? A1 : A0 — in front of every flop, as in the diagram.

With en=1, D gets the new shifted value. With en=0, D gets Q back, so the flop reloads what it already had. Held.

And that is precisely the 16 mux2_1 cells — one per flop. The third block is the real thing from your netlist. You can read the shift register straight off the page: bit 0's mux takes external A, bit 1's takes a_reg[0], bit 2's takes a_reg[1]… each stage fed by its neighbour, with each flop's own output wired to A0 as the hold path. That chain is "enabled shift register" in netlist form.

The adder itself needs no clock — you are right. It is a lump of gates, permanently computing. If you could wiggle a_reg and b_reg directly with your fingers, sum would follow with no clock anywhere in sight.

The clock is needed for the parts around it:

1. Something has to hold a and b steady. The adder's inputs come from flip-flops. Those flops are what need clocking. The adder is a passive consumer of whatever they present.
2. Serial input needs a notion of "next". A is one wire delivering 8 bits over time. "Over time" requires a heartbeat that defines when one bit ends and the next begins. That is the clock.
3. Combinational logic is briefly wrong. When a_reg changes, the carry ripples through the adder gate by gate, and for a few hundred picoseconds sum shows meaningless intermediate garbage before settling. Flip-flops paper over this: they only sample at clock edges, and the clock period is chosen to exceed the worst-case settling time.

That third point is the fundamental discipline of synchronous design: let combinational logic settle, then latch it. Combinational logic does the computing, flip-flops do the remembering, and the clock says when it is safe to move from one to the other.

Why this module

The hierarchy points at it. adder_demo instantiates the other three (L42, L47, L52, L56); nothing instantiates adder_demo. That makes it the top module — the root of the tree, the outermost box. Its ports are the boundary of the design; everything else is internal plumbing between sub-boxes. In a real flow you also explicitly tell the tool -top adder_demo.

And hierarchy is fictional anyway. Module boundaries are an organisational convenience for humans. Synthesis flattens them: the two shift_register instances get copied out and 32 loose cells end up in one flat pile. Open 01_netlist.v and there is exactly one module keyword — the sub-modules survive only as name prefixes like \sr_a/_16_. Even those prefixes are stripped by the GDS stage.

Physical pins exist only where silicon meets the outside world: bond pads wired out to package pins. There is simply nowhere for adder8's ports to physically be.

The 6-vs-16 point

Pins are genuinely scarce and expensive. Each needs a bond pad, a package pin and a board trace, and pads are enormous compared to logic cells. This design has six: clk, rst_n, A, B, S, en.

But the circuit needs 16 bits of input data — 8 for a_reg, 8 for b_reg. With six pins you cannot have 16 data wires. Two options:

• Parallel — 16 dedicated input pins, all bits arriving at once. Fast, wastefully wide.
• Serial — 2 pins (A, B), one bit each per clock cycle, 8 cycles to fill both registers. This is what the design does.

Serialising is trading time for pins. The shift registers are the mechanism: they accept a dribble of bits over 8 cycles and turn it into a wide parallel value the adder can consume in one go. Same trade-off as SPI, I²C or USB versus a 64-bit parallel bus.

Widths are declared, never inferred

Verilog does no type inference. Widths are always explicit or defaulted — and here is the correction worth internalising: A and B are not 8 bits. They are 1 bit each.

On L34, input wire A has no [x:y], so it defaults to a single bit — one physical wire, carrying one bit per clock cycle.

The 8 comes from the register, on L6: [7:0] declares a vector — indices 7 down to 0, so 8 bits, MSB at 7 and LSB at 0. The convention is [MSB:LSB], descending. And sum is [8:0], one wider, for the carry.

So the shape is: A and B are each one wire carrying a serial bit-stream. The eight-bit-ness lives in the shift register that accumulates them, not in the pin.

Which direction the stream fills the register is decided by the concatenation on L12 — worth working out yourself from first principles, since it determines your bit ordering and therefore your answer.

Yes, .clk(clk) is the connection syntax

It is called a named port connection. Read .clk(clk) as "connect the port named clk to my local signal named clk." Those are two different namespaces that happen to share a name; .serial_in(A) shows the general case. The breakdown is in the next block.

The alternative is positional — shift_register sr_a (clk, rst_n, en, A, a_reg); — which depends on port order and goes silently wrong the moment anyone reorders the port list. Always use named.

dfrtp

d-flip-flop, reset, true output, positive edge. Related cells in the same library follow the same scheme:

The full catalogue is the SkyWater PDK cell reference — worth bookmarking, you will be looking up cell names constantly while decoding puzzle.gds.

A net is a physical electrical connection — a wire, or more precisely a set of pins all shorted together at the same voltage. "Net" is the netlist word for it; wire is the Verilog word for the same thing. A netlist is literally the list of nets: which cell pins connect to which. That is all a circuit fundamentally is — cells plus nets.

As for how I know these are internal: it is pure scoping. Ports are the names listed between the ( on L31 and the ) on L38, each tagged input or output. a_reg, b_reg and sum appear after the port list closes, with no direction keyword — so they are local declarations, visible only inside adder_demo. Same rule as local variables inside a function.

Their job is to connect one instance's output to another's input: L44 has sr_a driving a_reg, and L53 has add0 consuming it. Purely internal plumbing. In silicon they are real copper traces between cells, but they never reach a pad.